Memory devices for non-volatile storage of information have been widely in use. Examples of such memory devices include read only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash EEPROM.
A flash memory generally refers to a flash EEPROM, which may be erased in blocks of data instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that the BIOS can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in devices such as modems because a flash memory allows these devices to be updated to support, for example, new protocols as they become standardized.
A flash memory device generally includes an array of memory cells arranged in rows and columns. Each memory cell includes a MOS transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. The gate corresponds to a word line and the drain and the source correspond to bit lines of the memory array. The gate of a conventional memory cell is generally a dual-gate structure, including a control gate and a floating gate, wherein the floating gate is sandwiched between two dielectric layers to trap carriers such as electrons, thereby “program” the cell. In other words, in a conventional cell, a first dielectric layer is formed over the channel, the floating gate is formed over the first dielectric layer, a second dielectric layer is formed over the floating gate, and the control gate is finally formed over the second dielectric layer.
During programming, a set of programming biases are applied to selected word lines and bit lines. One or more memory cells corresponding to the selected word lines and bit lines are biased in the programming state. For a single memory cell, different biases applied to the source and drain thereof creates an electric field along the channel thereof, through which electrons gain enough energy. Such hot electrons then tunnel through the first dielectric layer into the floating gate and become stored therein. As a result of the stored electrons in the floating gate, the threshold voltage of the memory cell is modified. The changing of the threshold voltage determines whether the memory cell is programmed.
To read a memory cell, reading biases are applied and a sensing device reads a current passing through the memory cell. If a memory cell is programmed, or has electrons stored in its floating gate, its current level is different from those memory cells which are not programmed. Therefore, based on the measured current level, the sensing device is capable of determining the state of each memory cell.
To erase the information stored in a flash memory, erasing biases are applied thereto to force the stored electrons to tunnel out of the floating gate, through a well-known mechanism in Fowler-Nordheim (F-N) tunneling.
However, certain problems are associated with a conventional flash memory, such as high power consumption, program and read disturbances. High power consumption is due to high program and erasure voltages required to induce electron tunneling for program and erase operations. Program and read disturbances relate to current leakage occurring to the non-selected neighboring memory cells while programming or reading a certain memory cell.
A disturbance in a flash memory array generally refers to a phenomenon when one selected cell in the memory array is being read or programmed, another programmed memory cell sharing the same word line or bit line may experience current leakage caused by electron tunneling of the selected cell, and a loss of electrons stored in the floating gate may result in a change of status from “programmed” to “erased”. The read disturbance may be explained with reference to FIG. 1, which shows a flash memory array comprising conventional floating gate memory cells.
Referring to FIG. 1, a flash memory array 100 includes a plurality of word lines WL1, WL2 . . . WL6, and a plurality of bit lines BL1, BL2, . . . , BL5. Each intersection of the word lines and bit lines define a memory cell. Each of the memory cells also includes a floating gate (not shown). As indicated, a memory cell A corresponding to word line WL3 and bit lines BL2 and BL3 is selected by biasing the corresponding word line and bit lines. For example, word line WL3 is biased at 3V, bit line BL2 is biased at 0.3V, and bit line BL3 is biased at 1.5V. Word lines WL1, WL2, WL4, WL5, and WL6 are grounded (0V), and bit lines BL1, BL4, and BL5 are unbiased, or floating (F). Under such biasing conditions, the information stored in cell A may be read.
Meanwhile, the memory cells sharing the same word line or bit line with cell A are also under certain biases. For example, cell B shares the same word line WL3 and bit line BL2 with cell A. Therefore, assuming bit line BL2 corresponds to the drain of cell B, an electric field exists between the gate and the drain of cell B, which induces a leakage current through cell B. The leakage current through cell B depends on the threshold voltage thereof, which depends upon the electron density in the floating gate thereof. A lower threshold voltage will result in a higher leakage current. Similarly, cells C and D may experience current leakages due to the biases at bit line BL2 and bit line BL3, respectively. The leakage currents through the neighboring cells, e.g., cells B, C, and D, will flow through bit lines BL2 and BL3, and may generate sensing errors of cell A.